1. Field of the Invention
The present invention relates to data processing systems for processing data using computers or the like, and more particularly to a data processing system having a data processor which can process outer abnormal signals transmitted during generation of the abnormal state.
2. Description of the Prior Art
In general, a data processing system using computers or the like, as shown in a block constitution diagram of FIG. 1, broadly comprises a central control unit (hereinafter referred to as a "controller") 1 such as computer, and a data processing unit (hereinafter referred to as "data processor") 2 connected to the controller 1. Command signal 3 and response signal 4 are transmitted or received between the controller 1 and the data processor 2.
Operation of the data processing system in FIG. 1 will now be described. The controller 1 usually transmits the command signal 3 to the data processor 2 represented by computer peripheral equipment such as a fixed disk and receives the response signal 4 from the data processor 2 so as to control the transmission and receiving of data. Electronics products in recent years are likely to adopt a control system using intelligent command to an object to be controlled as above described.
When an abnormal signal is inputted from outside to the data processor 2 of the data processing system, in the prior art, the abnormal signal is processed by a constitution shown in FIG. 2 and FIG. 3. In FIG. 2, the data processor 2 is composed of a data processing device 5 and a data control device 6. During generation of the abnormal signal, an outer abnormal signal 7 generated accidentally at the data processing device 5 is transmitted from the data processing device 5 to the data control device 6. The data control device 6 controls the data processing function of the data processing device 5, and also has function of rapidly detecting the outer abnormal signal 7 and studying the cause, storing it in inner reduction and sorting, and preparing to transmit the response signal to the command signal 3 subsequently transmitted from the controller 1.
Operation based on the above constitution will be described. In the usual apparatus, in order to inform generation of the abnormal state to the controller 1 rapidly, the data control device 6 of the data processor 2 receives the outer abnormal signal 7 as an interrupt signal and interrupts the partial operation and performs the abovementioned abnormal state processing operation, and transmits an attention signal 8 which is a response signal separate from the response signal 4 into the controller 1. In response to the attention signal 8, the controller 1 transmits the command signal 3 in order to detect how the abnormal state is generated, and a response signal is generated from the data processor 2 in response to the command signal 3. Thereby the abnormal state is dealt with.
The data control device 6 for processing the outer abnormal signal 7 is constituted as shown in FIG. 3. The data control device 6 comprises a microcomputer 9 for receiving the command signal 3 and performing control for the data processing, and an external extraordinary signal introducing portion 10 such as an interrupt controller functioning as input means of the microcomputer 9 to plural accidental outer abnormal conditions. For example, I8085 of Intel is preferable as the microcomputer 9, and I8259 of Intel is preferable as the external extraordinary signal introducing portion 10.
Operation of the data control device 6 having the above detailed constitution will be described. The external extraordinary signal introducing portion 10 is constituted concretely by an integrated circuit (hereinafter referred to as "IC") for example, and is preferable to introduce generation of plural external abnormal conditions into the microcomputer 9 for processing. In other words, the external extraordinary signal introducing portion 10 supplies the start address for the program execution to the microcomputer 9 so that the microcomputer 9 stores generation of the external abnormal conditions and executes the processing from that of high priority. The start address of the program is different, of course, depending on the nature of the external abnormal condition. The microcomputer 9 executes the processing of the abnormal conditions based on signals from the external extraordinary signal introducing portion 10 and then outputs the attention signal 8 to the controller 1.
Normally, the task of the interrupt processing in the microcomputer 9 is executed so that the microcomputer 9 interrupts the task during execution. However, if there is no interrupt due to generation of external abnormal condition, of course, the task is executed continuously.
In the above-mentioned data processor in the prior art, as an example of hardware constitution for executing the data processing of the external abnormal signal 7 as interrupt signal when abnormal condition is generated, an external circuit is connected to the microcomputer 9 or the microcomputer 9 itself must have the interrupt processing function. The technical idea is disclosed in "Guide to Microcomputer (second edition)" p. 173, written by Iwao Morishita and published by Shokodo. Also in p. 195-197 of the book, a data processor with a priority interrupt controller is disclosed as another example of hardware constitution and an automatic priority interrupt mode is described as an example of operation of the data processor.
According to the data processing system having the above-mentioned constitution in the prior art, there are various problems as follows.
First, when the abnormal condition is generated outside of the data processor, the microcomputer 9 must have the interrupt processing function for interrupting the task during execution and processing the external abnormal signal. In order to prevent bad influence due to the interruption of the task in the microcomputer 9, a complicated external circuit must be added to the microcomputer 9 and the complicated task control must be performed by the external circuit.
The external extraordinary signal introducing portion 10 comprising an interrupt controller exclusive for the microcomputer 9 must be installed. The interrupt controller to constitute the external extraordinary signal introducing portion 10 is not a general purpose item, and moreover the IC employed as the interrupt controller is expensive in comparison to that in general use. Particularly, when the priority interrupt controller with LSI (large scale integrated circuit) assembled thereto is used, the manufacturing cost of the data processing system is significantly increased.